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psoc ? 4: psoc 4000 family datasheet programmable system-on-chip (psoc ? ) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-89638 rev. *e revised may 26, 2015 general description psoc ? 4 is a scalable and reconfigurable platfo rm architecture for a fami ly of programmable embedde d system controllers with an arm ? cortex?-m0 cpu. it combines programmable and reconfigurable analog and digital blocks with flex ible automatic routing. the psoc 4000 product family is the smallest member of the psoc 4 pl atform architecture. it is a combination of a microcontroller wi th standard communication and timing peripherals, a capacitive t ouch-sensing system (capsense) with best-in-class performance, and general-purpose analog. psoc 4000 products will be fully upward co mpatible with members of the psoc 4 platform for new applica- tions and design needs. features 32-bit mcu subsystem 16-mhz arm cortex-m0 cpu up to 16 kb of flash with read accelerator up to 2 kb of sram programmable analog two current dacs (idacs) for ge neral-purpose or capacitive sensing applications one low-power comparator with internal reference low power 1.71-v to 5.5-v operation deep sleep mode with wake-up on interrupt and i 2 c address detect capacitive sensing cypress capsense sigma-delta (csd) provides best-in-class signal-to-noise ratio (snr) and water tolerance cypress-supplied software component makes capacitive sensing design easy automatic hardware tuning (smartsense?) over a sensor range of 5 pf to 45 pf serial communication multi-master i 2 c block with the ability to do address matching during deep sleep and generate a wake-up on match timing and pulse-width modulation one 16-bit timer/counter/pu lse-width modulator (tcpwm) block center-aligned, edge, and pseudo-random modes comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications up to 20 programmable gpio pins 28-pin ssop, 24-pin qfn, 16-pin soic, 16-pin qfn, 16 ball wlcsp, and 8-pin soic packages gpio pins on ports 0, 1, and 2 can be capsense or have other functions drive modes, strengths, and slew rates are programmable psoc creator design environment integrated development environment (ide) provides schematic design entry and build (with analog and digital automatic routing) applications programming interface (api) component for all fixed-function and programmable peripherals industry-standard tool compatibility after schematic entry, development can be done with arm-based industry-stand ard development tools
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 2 of 34 more information cypress provides a wealth of data at www.cypress.com to help you to select the right psoc device for your design, and to help you to quickly and effectively integrate the device into your design. for a comprehensive list of resources, see the knowledge base article kba86521, how to design with psoc 3, psoc 4, and psoc 5lp . following is an abbreviated list for psoc 4: overview: psoc portfolio , psoc roadmap product selectors: psoc 1 , psoc 3 , psoc 4 , psoc 5lp in addition, psoc creator includes a device selection tool. application notes: cypress offers a large number of psoc application notes covering a bro ad range of topics, from basic to advanced level. recommended application notes for getting started with psoc 4 are: ? an79953 : getting started with psoc 4 ? an88619: psoc 4 hardware design considerations ? an86439: using psoc 4 gpio pins ? an57821: mixed signal circuit board layout ? an81623: digital design best practices ? an73854: introduction to bootloaders ? an89610: arm cortex code optimization technical reference manual (trm) is in two documents: ? architecture trm details each psoc 4 functional block. ? registers trm describes each of the psoc 4 registers. development kits: ? cy8ckit-040, psoc 4000 pioneer kit, is an easy-to-use and inexpensive development platform with debugging capability. this kit includes connectors for arduino? compatible shields and digilent ? pmod? daughter cards. ? the miniprog3 device provides an interface for flash programming and debug. psoc creator psoc creator is a free windows-based integrated design environment (i de). it enables concurrent hardware and firmware design of psoc 3, psoc 4, and psoc 5lp based systems. create designs usin g classic, familiar schematic capture supported by over 100 pre-verified, production-ready psoc components; see the list of component datasheets . with psoc creator, you can: 1. drag and drop component icons to build your hardware system design in the main design workspace 2. codesign your application firm ware with the psoc hardware, using the psoc creator ide c compiler 3. configure components using the configuration tools 4. explore the library of 100+ components 5. review component datasheets figure 1. capsense example project in psoc creator 1 2 4 5 5 3
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 3 of 34 contents functional definition........................................................ 5 cpu and memory subsystem ..................................... 5 system resources ...................................................... 5 analog blocks.............................................................. 6 fixed function digital........... ....................................... 6 gpio ........................................................................... 6 special function peripherals... .............. .............. ........ 6 pinouts .............................................................................. 7 power............................................................................... 12 unregulated external supply... .............. .............. ...... 12 regulated external supply........................................ 12 development support .................................................... 13 documentation .......................................................... 13 online ........................................................................ 13 tools.......................................................................... 13 electrical specifications ................................................ 14 absolute maximum ratings..... .................................. 14 device level specifications....................................... 14 analog peripherals .... .............. .............. .............. ...... 17 digital peripherals .... .............. .............. .............. ....... 19 memory ..................................................................... 20 system resources .................................................... 20 ordering information...................................................... 23 part numbering conventions ... ................................. 23 packaging........................................................................ 25 package outline drawings ........................................ 26 acronyms ........................................................................ 30 document conventions ................................................. 32 units of measure ....................................................... 32 revision history ............................................................. 33 sales, solutions, and legal information ...................... 34 worldwide sales and design supp ort............. .......... 34 products .................................................................... 34 psoc? solutions ...................................................... 34 cypress developer community................................. 34 technical support ................. .................................... 34
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 4 of 34 figure 2. block diagram psoc 4000 devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. the arm serial-wire debug (swd) interface supports all programming and debug features of the device. complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. it does not require special interfaces, debugging pods, simulators, or emulators. only the standard programming connections are required to fully support debug. the psoc creator ide provides fully integrated programming and debug support for the psoc 4000 devices. the swd interface is fully compatible with industry-standard third-party tools. the psoc 4000 family provides a level of security not possible with multi-chip application solutions or with microcon- trollers. it has the following advantages: allows disabling of debug features robust flash protection allows customer-proprietary fu nctionality to be implemented in on-chip programmable blocks the debug circuits are enabled by default and can only be disabled in firmware. if they are not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the de vice with new firmware that enables debugging. additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. all programming, debug, and test interfaces are disabled when maximum device security is enabled. therefore, psoc 4000, with device security enabled, may not be returned for failure analysis. this is a trade-off the psoc 4000 allows the customer to make. deep sleep active/ sleep cpu subsystem sram 2 kb sram controller rom 4 kb rom controller flash 16 kb read accelerator spcif swd/tc nvic, irqmx cortex m0 16 mhz mul system interconnect ( single/multi layer ahb ) i/o subsystem 20 x gpios ioss gpio (4x ports) peripherals peripheral interconnect (mmio) pclk psoc 4000 32-bit ahb- lite dft logic test dft analog system resources lite power clock wdt ilo reset clock control imo sleep control pwrsys ref por wic reset control xres 1x scb- i2c capsense high speed i/o matrix power modes 1x tcpwm
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 5 of 34 functional definition cpu and memory subsystem cpu the cortex-m0 cpu in the psoc 40 00 is part of the 32-bit mcu subsystem, which is optimized for low-power operation with extensive clock gating. most instruct ions are 16 bits in length and the cpu executes a su bset of the thumb-2 instruction set. this enables fully compatible, binary, upward migration of the code to higher performance processors, such as the cortex-m3 and m4. it includes a nested vectored interrupt controller (nvic) block with eight interrupt inputs and also includes a wakeup interrupt controller (wic). the wic can wake the processor from the deep sleep mode, allowing power to be switched off to the main processor when the chip is in the deep sleep mode. the cpu subsystem also includes a 24-b it timer called systick, which can generate an interrupt. the cpu also includes a debug interface, the serial wire debug (swd) interface, which is a 2-wire form of jtag. the debug configuration used for psoc 4000 has four breakpoint (address) comparators and two watchpoint (data) comparators. flash the psoc 4000 device has a flash module with a flash accel- erator, tightly coupled to the cpu to improve average access times from the flash block. the low-power flash block is designed to deliver zero wait-state (ws) access time at 16 mhz. sram two kb of sram are provided with zero wait-state access at 16 mhz. srom a supervisory rom that contains boot and configuration routines is provided. system resources power system the power system is described in detail in the section on power on page 12 . it provides an assurance that voltage levels are as required for each respective mode and either delays mode entry (for example, on power-on reset (por)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detecti on). the psoc 4000 operates with a single external supply ov er the range of either 1.8 v 5% (externally regulated) or 1.8 to 5.5 v (internally regulated) and has three different power modes, transitions between which are managed by the power system. the psoc 4000 provides active, sleep, and deep sleep low-power modes. all subsystems are operational in active mode. the cpu subsystem (cpu, flash, and sram) is clock-gated off in sleep mode, while all peripherals and interrupts are active with instan- taneous wake-up on a wake-up event. in deep sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes 35 s. clock system the psoc 4000 clock system is re sponsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glit ching. in addition, the clock system ensures that there ar e no metastable conditions. the clock system for the psoc 4000 c onsists of the internal main oscillator (imo) and the internal low-frequency oscillator (ilo) and provision for an external clock. figure 3. psoc 4000 mcu clocking architecture the f cpu signal can be divided down to generate synchronous clocks for the analog and digital peripherals. there are four clock dividers for the psoc 4000, each with 16-bit divide capability the 16-bit capability allows flexible generation of fine-grained frequency values and is fully supported in psoc creator. imo clock source the imo is the primary source of internal clocking in the psoc 4000. it is trimmed during testing to achieve the specified accuracy.the imo default frequency is 24 mhz and it can be adjusted from 24 to 48 mhz in steps of 4 mhz. the imo tolerance with cypress-provided calibration settings is 2% (24 and 32 mhz). ilo clock source the ilo is a very low power, 40-khz oscillator, which is primarily used to generate clocks for the watchdog timer (wdt) and peripheral operation in deep sl eep mode. ilo-driven counters can be calibrated to the imo to improve accuracy. watchdog timer a watchdog timer is implemented in the clock block running from the ilo; this allows watchdog operation during deep sleep and generates a watchdog reset if not serviced before the set timeout occurs. the watchdog reset is recorded in a reset cause register, which is firmware readable. reset the psoc 4000 can be reset from a variety of sources including a software reset. reset events are asynchronous and guarantee reversion to a known state. the reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. an xres pin is reserved for external reset on the 24-pin package. an internal por is provided on the 16-pin and 8-pin packages. the xres pin has an internal pull-up resistor that is always enabled. reset is active low. voltage reference the psoc 4000 reference system generates all internally required references. a 1.2-v voltage reference is provided for the comparator. the idacs are based on a 5% reference. imo external clock f cpu ( connects to gpio pin p 0.4 ) divide by 2,4,8
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 6 of 34 analog blocks low-power comparators the psoc 4000 has a low-power comparator, which uses the built-in voltage reference. any one of up to 16 pins can be used as a comparator input and the out put of the comparator can be brought out to a pin. the selected comparator input is connected to the minus input of the comparator with the plus input always connected to the 1.2-v voltage re ference. this comparator is also used for capsense purposes and is not available during capsense operation. current dacs the psoc 4000 has two idacs, which can drive any of up to 16 pins on the chip. these idacs have programmable current ranges. analog multiplexed buses the psoc 4000 has two concentric independent buses that go around the periphery of the chip. these buses (called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal resources (idacs, comparator) to connect to any pin on ports 0, 1, and 2. fixed function digital timer/counter/pwm (tcpwm) block the tcpwm block consists of a 16-bit counter with user-programmable period length. t here is a capture register to record the count value at the ti me of an event (which may be an i/o event), a period register that is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals that are used as pwm duty cycle ou tputs. the block also provides true and complementary outputs with programmable offset between them to allow use as dead-band programmable complementary pwm outputs. it also has a kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an over-current state is indicated and the pwm driving the fets needs to be shut off immediately with no time for software intervention. serial communication block (scb) the psoc 4000 has a serial communication block, which imple- ments a multi-master i 2 c interface. i 2 c mode : the hardware i 2 c block implements a full multi-master and slave interface (it is capable of multi-master arbitration). this block is capable of operating at speeds of up to 400 kbps (fast mode) and has flexible buffering options to reduce interrupt overhead and latency for the cpu. it also supports ezi2c that creates a mailbox address range in the memory of the psoc 4000 and effectively reduces i 2 c commu- nication to reading from and writing to an array in memory. in addition, the block supports an 8-deep fifo for receive and transmit which, by increasing the time given for the cpu to read data, greatly reduces the need for clock stretching caused by the cpu not having read data on time. the i 2 c peripheral is compatible with the i 2 c standard-mode and fast-mode devices as defined in the nxp i 2 c-bus specification and user manual (um10204). the i 2 c bus i/o is implemented with gpio in open-drain modes. the psoc 4000 is not completely compliant with the i 2 c spec in the following respect: gpio cells are not overvoltage to lerant and, ther efore, cannot be hot-swapped or powered up independently of the rest of the i 2 c system. fast-mode minimum fall time is not met in fast strong mode; slow strong mode can help meet this spec depending on the bus load. gpio the psoc 4000 has up to 20 gpios. the gpio block imple- ments the following: eight drive modes: ? analog input mode (input and output buffers disabled) ? input only ? weak pull-up with strong pull-down ? strong pull-up with weak pull-down ? open drain with strong pull-down ? open drain with strong pull-up ? strong pull-up with strong pull-down ? weak pull-up with weak pull-down input threshold select (cmos or lvttl). individual control of input and output buffer enabling/disabling in addition to the drive strength modes selectable slew rates for dv/dt related noise control to improve emi the pins are organized in logica l entities called ports, which are 8-bit in width (less for ports 2 and 3). during power-on and reset, the blocks are forced to the disa ble state so as not to crowbar any inputs and/or cause excess turn-on current. a multiplexing network known as a high-speed i/o matrix is used to multiplex between various signals that may connect to an i/o pin. data output and pin state register s store, respectively, the values to be driven on the pins and the states of the pins themselves. every i/o pin can generate an interrupt if so enabled and each i/o port has an interrupt request (irq) and interrupt service routine (isr) vector associated with it (4 for psoc 4000). the 28-pin and 24-pin packages have 20 gpios. the 16-pin soic has 13 gpios. the 16-pin qfn and the 16-ball wlcsp have 12 gpios. the 8-pin soic has 5 gpios. special function peripherals capsense capsense is supported in the psoc 4000 through a csd block that can be connected to up to 16 pins through an analog mux bus via an analog switch (pins on port 3 are not available for capsense purposes). capsense function can thus be provided on any available pin or group of pins in a system under software control. a psoc creator com ponent is provided for the capsense block to make it easy for the user. shield voltage can be driven on another mux bus to provide water-tolerance capability. water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. proximity sensing can also be implemented. the capsense block has two idacs, which can be used for general purposes if capsense is not being used (both idacs are available in that case) or if capsense is used without water tolerance (one idac is available).
document number: 001-89638 rev. *e page 7 of 34 psoc ? 4: psoc 4000 family datasheet pinouts all port pins support gpio. ports 0, 1, and 2 support csd ca psense and analog multiplexed bus connections. tcpwm functions and alternate functions are multiplexed with port pins as follows for the five psoc 4000 packages. table 1. pin descriptions 28-pin ssop 24-pin qfn 16-pin qfn 16-pin soic 8-pin soic pin name pin name pin name pin name pin name tcpwm signals alternate functions 20 vss 21 p0.0/trin0 1 p0.0/trin0 trin0: trigger input 0 22 p0.1/trin1/cmpo _0 2 p0.1/trin1/cmpo _0 1 p0.1/trin1/cmpo _0 3 p0.1/trin1/cmpo _0 trin1: trigger input 1 cmpo_0: sense comp out 23 p0.2/trin2 3 p0.2/trin2 2 p0.2/trin2 4 p0.2/trin2 trin2: trigger input 2 24 p0.3/trin3 4 p0.3/trin3 trin3: trigger input 3 25 p0.4/trin4/cmpo _0/ext_clk 5 p0.4/trin4/cmpo _0/ext_clk 3 p0.4/trin4/cmpo _0/ext_clk 5 p0.4/trin4/cmpo _0/ext_clk 2 p0.4/trin4/cmpo _0/ext_clk trin4: trigger input 4 cmpo_0: sense comp out, external clock, cmod cap 26 vcc 6 vcc 4 vcc 6 vcc 3 vcc 27 vdd 7 vdd 6 vdd 7 vdd 4 vdd 28 vss 8 vss 7 vss 8 vss 5 vss 1 p0.5 9 p0.5 5 vddio 9 p0.5 2 p0.6 10 p0.6 8 p0.6 10 p0.6 3p0.711p0.7 4p1.012p1.0 5 p1.1/out0 13 p1.1/out0 9 p1.1/out0 11 p1.1/out0 6 p1.1/out0 out0: pwm out 0 6 p1.2/scl 14 p1.2/scl 10 p1.2/scl 12 p1.2/scl i2c clock 7 p1.3/sda 15 p1.3/sda 11 p1.3/sda 13 p1.3/sda i2c data 8 p1.4/und0 16 p1.4/und0 und0: underflow out 9 p1.5/ovf0 17 p1.5/ovf0 ovf0: overflow out 10 p1.6/ovf0/und0/n out0 /cmpo_0 18 p1.6/ovf0/und0/n out0 /cmpo_0 12 p1.6/ovf0/und0/n out0/cmpo_0 14 p1.6/ovf0/und0/n out0/cmpo_0 7 p1.6/ovf0/und0/n out0/cmpo_0 nout0: complement of out0, und0, ovf0 as above cmpo_0: sense comp out, internal reset function [1] note 1. must not have load to ground during por (should be an output).
document number: 001-89638 rev. *e page 8 of 34 psoc ? 4: psoc 4000 family datasheet descriptions of the pin functions are as follows: vdd : power supply for both analog and digital sections. vddio : where available, this pin provides a separate voltage domain (see the power section for details). vss : ground pin. vccd : regulated digital supply (1.8 v 5%). pins belonging to ports 0, 1, and 2 can all be used as csd sense or shield pins connected to amuxbus a or b. they can also be u sed as gpio pins that can be driven by the firmware, in addition to their al ternate functions listed in the ta b l e 1 . pins on port 3 can be used as gpio, in addi tion to their alternat e functions listed above. the following packages are provided: 28-pin ssop, 24-p in qfn, 16-pin qfn, 16-pin soic, and 8-pin soic. 11 vss 12 no connect (nc) [2] 13 p1.7/match/ext_ clk 19 p1.7/match/ext_ clk 13 p1.7/match/ext_ clk 15 p1.7/match/ext_ clk match: match out external clock 14 p2.0 20 p2.0 16 p2.0 15 vss 16 p3.0/sda/swd_io 21 p3.0/sda/swd_io 14 p3.0/sda/swd_io 1 p3.0/sda/swd_io 8 p3.0/sda/swd_io i2c data, swd i/o 17 p3.1/scl/swd_cl k 22 p3.1/scl/swd_cl k 15 p3.1/scl/swd_cl k 2 p3.1/scl/swd_cl k 1 p3.1/scl/swd_cl k i2c clock, swd clock 18 p3.2 23 p3.2 16 p3.2 out0:pwm out 0 19 xres 24 xres xres: external reset table 1. pin descriptions (continued) 28-pin ssop 24-pin qfn 16-pin qfn 16-pin soic 8-pin soic pin name pin name pin name pin name pin name tcpwm signals alternate functions note 2. this pin is not to be used; it must be left floating.
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 9 of 34 figure 4. 28- pin ssop pinout figure 5. 24-pin qfn pinout figure 6. 16-pin qfn pinout 28 ssop (top view) 10 11 28 27 26 25 23 22 21 20 19 18 17 2 3 4 5 6 7 8 9 1 12 13 14 16 15 24 vss nc p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 vss vdd vcc p0.4 p0.3 p0.2 p0.1 p0.0 vss xres p3.2 p3.1 p3.0 vss qfn 24 top view p0.5 xres 13 17 16 18 6 2 3 4 5 1 24 23 22 21 20 19 789 10 vdd vss p0.6 p0.7 p1.0 p3.2 p3.1 p3.0 p2.0 p1.7 vccd p0.0 p0.1 p1.4 p1.3 p1.2 p1.1 p1.6 p1.5 11 12 14 15 p0.2 p0.3 p0.4 qfn 16 top view p3.2 2 3 4 1 16 15 14 13 p3.1 p3.0 p1.7 p0.1 p0.2 p0.4 vccd 11 10 12 p1.2 p1.1 p1.6 p1.3 9 vss 567 8 vddio vdd p0.6
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 10 of 34 figure 7. 16-pin soic pinout figure 8. 8-pin soic pinout 1 2 3 4 5 6 7 8 10 11 12 13 14 p3.0 15 16 16-soic top view p3.1 p0.1 p0.2 p0.4 vccd vdd vss p0.5 p0.6 p1.1 p1.2 p1.3 p1.6 p1.7 p2.0 9 1 2 3 4 5 6 p3.1 7 8 p0.4 vccd vdd vss p1.1 p1.6 p3.0 8 - soic top view
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 11 of 34 note 3. must not have load to ground during por (should be an output). table 2. 16-ball wlcsp pin descriptions and diagram pin name tcpwm signal alternate functions pin diagram b4 p3.2 out0:pwmout0 ? bottom view top view c3 p0.2/trin2 trin2:trigger input 2 ? c4 p0.4/trin4/cmpo_0/ ext_clk trin4:trigger input 4 cmpo_0: sense comp out, ext. clock, cmod cap d4 vccd ? ? d3 vdd ? ? d2 vss ? ? c2 vddio ? ? d1 p0.6 ? ? c1 p1.1/out0 out0:pwmout0 ? b1 p1.2/scl ? i 2 c clock a1 p1.3/sda ? i 2 c data a2 p1.6/ovf0/und0/no ut0/cmpo_0 nout0:complement of out0, und0, ovf0 cmpo_0: sense comp out, internal reset function [3] b2 p1.7/match/ ext_clk match: match out external clock a3 p2.0 ? ? b3 p3.0/sda/swd_io ? i 2 c data, swd i/o a4 p3.1/scl/swd_clk ? i 2 c clock, swd clock 4 d c b a 321 4 d c b a 3 2 1 pin 1 dot
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 12 of 34 power the following power system diagrams ( figure 9 and figure 10 ) show the set of power supply pins as implemented for the psoc 4000. the system has one regulator in active mode for the digital circuitry. there is no analog regulator; the analog circuits run directly from the v dd input. there is a separate regulator for the deep sleep mode. the supply voltage range is either 1.8 v 5% (externally regulated) or 1. 8 v to 5.5 v (unregulated exter- nally; regulated internally) with all functions and circuits operating over that range. the v ddio pin, available in the 16-pin qfn package, provides a separate voltage domain for the following pins: p3.0, p3.1, and p3.2. p3.0 and p3.1 can be i 2 c pins and the chip can thus communicate with an i 2 c system, running at a different voltage (where v ddio ? v dd ). for example, v dd can be 3.3 v and v ddio can be 1.8 v. the psoc 4000 family allows two distinct modes of power supply operation: unregulated external supply and regulated external supply. unregulated external supply in this mode, the psoc 4000 is powered by an external power supply that can be anywhere in the range of 1.8 to 5.5 v. this range is also designed for battery-powered operation. for example, the chip can be powered from a battery system that starts at 3.5 v and works down to 1.8 v. in this mode, the internal regulator of the psoc 4000 supplies the internal logic and the v ccd output of the psoc 4000 must be bypassed to ground via an external capacitor (0.1 f; x5r ceramic or better). bypass capacitors must be used from v dd to ground. the typical practice for systems in this frequency range is to use a capacitor in the 1-f range, in parallel with a smaller capacitor (0.1 f, for example). note that these are simply rules of thumb and that, for critical applications, the pcb layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. an example of a bypass scheme follows (v ddio is available on the 16-qfn package). figure 9. 16-pin qfn bypass scheme example - unregulated external supply regulated external supply in this mode, the psoc 4000 is powered by an external power supply that must be within the ra nge of 1.71 to 1.89 v; note that this range needs to include the power supply ripple too. in this mode, the v dd and v ccd pins are shorted together and bypassed. the internal regulator should be disabled in the firmware. note that in this mode vdd (vccd) should never exceed 1.89 in any condition, including flash programming. an example of a bypass scheme follows (v ddio is available on the 16-qfn package). figure 10. 16-pin qfn bypass scheme example - regulated external supply psoc 4000 v dd v ddio v ss 1.71 v < v ddio v dd 1.8 v to 5.5 v 0. 1 f 0.1 ? f v ccd 0. 1 f power supply connections when 1.8 v dd 5. 5 v 1 f ? ? ? ? ? ? psoc 4000 v dd v ddio v ss 0.1 ? f v ccd 0.1 ? f power supply connections when 1.71 ? v dd ? 1. 89 v 1 ? f 1.71 v to 1.89 v 1.71 v < v ddio < v dd
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 13 of 34 development support the psoc 4000 family has a rich set of documentation, devel- opment tools, and online resources to assist you during your development process. visit www.cypress.com/go/psoc4 to find out more. documentation a suite of documentation supports the psoc 4000 family to ensure that you can find answers to your questions quickly. this section contains a list of some of the key documents. software user guide : a step-by-step guide for using psoc creator. the software user guide shows you how the psoc creator build process works in detail, how to use source control with psoc creator, and much more. component datasheets : the flexibility of psoc allows the creation of new peripherals (components) long after the device has gone into production. component data sheets provide all of the information needed to select and use a particular component, including a functional description, api documentation, example code, and ac/dc specifications. application notes : psoc application notes discuss a particular application of psoc in depth; examples include brushless dc motor control and on-chip filter ing. application notes often include example projects in addition to the application note document. technical reference manual : the technical reference manual (trm) contains all the technical detail you need to use a psoc device, including a comp lete description of all psoc registers. the trm is available in the documentation section at www.cypress.com/psoc4. online in addition to print documentation, the cypress psoc forums connect you with fellow psoc user s and experts in psoc from around the world, 24 hours a day, 7 days a week. tools with industry standard cores, programming, and debugging interfaces, the psoc 4000 family is part of a development tool ecosystem. visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use psoc creator ide, supported third party compilers, programmers, debuggers, and development kits.
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 14 of 34 electrical specifications absolute maximum ratings device level specifications all specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specific ations are valid for 1.71 v to 5.5 v, except where noted. note 4. usage above the absolute maximum conditions listed in table 1 may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods of time may affect device reliability. the maximum storage temperature is 150 c in compliance with jedec standard jesd 22-a103, high temperature storage life. when used below absolute maximum conditions but a bove normal operating conditions, the device may not operate to specification. table 3. absolute maximum ratings [4] spec id# parameter description min typ max units details/ conditions sid1 v dd_abs digital supply relative to v ss ?0.5 ? 6 v sid2 v ccd_abs direct digital core voltage input relative to v ss ?0.5 ? 1.95 v sid3 v gpio_abs gpio voltage ?0.5 ? v dd +0.5 v sid4 i gpio_abs maximum current per gpio ?25 ? 25 ma sid5 i gpio_injection gpio injection current, max for v ih > v dd , and min for v il < v ss ?0.5 ? 0.5 ma current injected per pin bid44 esd_hbm electrostatic discharge human body model 2200 ? ? v bid45 esd_cdm electrostatic discharge charged device model 500 ? ? v bid46 lu pin current for latch-up ?140 ? 140 ma table 4. dc specifications typical values measured at v dd = 3.3 v and 25 c. spec id# parameter description min typ max units details/ conditions sid53 v dd power supply input voltage 1.8 ? 5.5 v with regulator enabled sid255 v dd power supply input voltage (v ccd = v dd ) 1.71 ? 1.89 v internally unreg- ulated supply sid54 v ddio v ddio domain supply 1.71 ? v dd v sid55 c efc external regulator voltage bypass ? 0.1 ? f x5r ceramic or better sid56 c exc power supply bypass capacitor ? 1 ? f x5r ceramic or better active mode, v dd = 1.8 to 5.5 v sid9 i dd5 execute from flash; cpu at 6 mhz ? 2.0 2.85 ma sid12 i dd8 execute from flash; cpu at 12 mhz ? 3.2 3.75 ma sid16 i dd11 execute from flash; cpu at 16 mhz ? 4.0 4.5 ma sleep mode, v dd = 1.71 to 5.5 v sid25 i dd20 i 2 c wakeup, wdt on. 6 mhz ? 1.1 ? ma sid25a i dd20a i 2 c wakeup, wdt on. 12 mhz ? 1.4 ? ma deep sleep mode, v dd = 1.8 to 3.6 v (regulator on) sid31 i dd26 i 2 c wakeup and wdt on ? 2.5 8.2 a
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 15 of 34 gpio deep sleep mode, v dd = 3.6 to 5.5 v (regulator on) sid34 i dd29 i 2 c wakeup and wdt on ? 2.5 12 a deep sleep mode, v dd = v ccd = 1.71 to 1.89 v (regulator bypassed) sid37 i dd32 i 2 c wakeup and wdt on ? 2.5 9.2 a xres current sid307 i dd_xr supply current while xres asserted ? 2 5 ma table 4. dc specifications (continued) typical values measured at v dd = 3.3 v and 25 c. spec id# parameter description min typ max units details/ conditions table 5. ac specifications spec id# parameter description min typ max units details/ conditions sid48 f cpu cpu frequency dc ? 16 mhz 1.71 ?? v dd ?? 5.5 sid49 [5] t sleep wakeup from sleep mode ? 0 ? s sid50 [5] t deepsleep wakeup from deep sleep mode ? 35 ? s notes 5. guaranteed by characterization. 6. v ih must not exceed v dd + 0.2 v. table 6. gpio dc specifications (referenced to v ddio for 16-pin qfn v ddio pins) spec id# parameter description min typ max units details/ conditions sid57 v ih [6] input voltage high threshold 0.7 v dd ?? vcmos input sid58 v il input voltage low th reshold ? ? 0.3 v dd vcmos input sid241 v ih [6] lvttl input, v dd < 2.7 v 0.7 v dd ?? v sid242 v il lvttl input, v dd < 2.7 v ? ? 0.3 v dd v sid243 v ih [6] lvttl input, v dd ? 2.7 v 2.0 ? ? v sid244 v il lvttl input, v dd ? 2.7 v ? ? 0.8 v sid59 v oh output voltage high level v dd ?0.6 ? ? v i oh = 4 ma at 3v v dd sid60 v oh output voltage high level v dd ?0.5 ? ? v i oh = 1 ma at 1.8 v v dd sid61 v ol output voltage low level ? ? 0.6 v i ol = 4 ma at 1.8 v v dd sid62 v ol output voltage low level ? ? 0.6 v i ol = 10 ma at 3v v dd sid62a v ol output voltage low level ? ? 0.4 v i ol = 3ma at 3v v dd sid63 r pullup pull-up resistor 3.5 5.6 8.5 k ? sid64 r pulldown pull-down resistor 3.5 5.6 8.5 k ? sid65 i il input leakage current (absolute value) ? ? 2 na 25 c, v dd = 3.0 v sid66 c in input capacitance ? 3 7 pf
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 16 of 34 sid67 [7] v hysttl input hysteresis lvttl 15 40 ? mv v dd ? 2.7 v sid68 [7] v hyscmos input hysteresis cmos 0.05 v dd ??mvv dd < 4.5 v sid68a [7] v hyscmos5v5 input hysteresis cmos 200 ? ? mv v dd > 4.5 v sid69 [7] i diode current through protection diode to v dd /v ss ??100 a sid69a [7] i tot_gpio maximum total source or sink chip current ??85ma table 6. gpio dc specifications (referenced to v ddio for 16-pin qfn v ddio pins) (continued) spec id# parameter description min typ max units details/ conditions note 7. guaranteed by characterization. table 7. gpio ac specifications (guaranteed by characterization) spec id# parameter description min typ max units details/ conditions sid70 t risef rise time in fast strong mode 2 ? 12 ns 3.3 v v dd , cload = 25 pf sid71 t fallf fall time in fast strong mode 2 ? 12 ns 3.3 v v dd , cload = 25 pf sid72 t rises rise time in slow strong mode 10 ? 60 ? 3.3 v v dd , cload = 25 pf sid73 t falls fall time in slow strong mode 10 ? 60 ? 3.3 v v dd , cload = 25 pf sid74 f gpiout1 gpio f out ; 3.3 v ? v dd ?? 5.5 v. fast strong mode. ? ? 16 mhz 90/10%, 25 pf load, 60/40 duty cycle sid75 f gpiout2 gpio f out ; 1.71 v ?? v dd ?? 3.3 v. fast strong mode. ? ? 16 mhz 90/10%, 25 pf load, 60/40 duty cycle sid76 f gpiout3 gpio f out ; 3.3 v ?? v dd ?? 5.5 v. slow strong mode. ? ? 7 mhz 90/10%, 25 pf load, 60/40 duty cycle sid245 f gpiout4 gpio f out ; 1.71 v ?? v dd ?? 3.3 v. slow strong mode. ? ? 3.5 mhz 90/10%, 25 pf load, 60/40 duty cycle sid246 f gpioin gpio input operating frequency; 1.71 v ?? v dd ?? 5.5 v ? ? 16 mhz 90/10% v io
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 17 of 34 xres analog peripherals comparator note 8. guaranteed by characterization. table 8. xres dc specifications spec id# parameter description min typ max units details/ conditions sid77 v ih input voltage high threshold 0.7 v dd ? ? v cmos input sid78 v il input voltage low threshold ? ? 0.3 v dd v cmos input sid79 r pullup pull-up resistor 3.5 5.6 8.5 k ? sid80 c in input capacitance ? 3 7 pf sid81 [8] v hysxres input voltage hysteresis ? 0.05* v dd ? mv typical hysteresis is 200 mv for v dd > 4.5v table 9. xres ac specifications spec id# parameter description min typ max units details/ conditions sid83 [8] t resetwidth reset pulse width 5 ? ? s bid#194 [8] t resetwake wake-up time from reset release ? ? 3 ms table 10. comparator dc specifications spec id# parameter description min typ max units details/ conditions sid330 [8] i cmp1 block current, high bandwidth mode ? ? 110 a sid331 [8] i cmp2 block current, low power mode ? ? 85 a sid332 [8] v offset1 offset voltage, high bandwidth mode ? 10 30 mv sid333 [8] v offset2 offset voltage, low power mode ? 10 30 mv sid334 [8] z cmp dc input impedance of comparator 35 ? ? m ? sid338 [8] vinp_comp comparator input range 0 ? 3.6 v max input voltage is lower of 3.6 v or v dd sid339 vref_comp comparator internal voltage reference 1.188 1.2 1.212 v
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 18 of 34 csd table 11. comparator ac specifications (guaranteed by characterization) spec id# parameter description min typ max units details/ conditions sid336 [8] t comp1 response time high bandwidth mode, 50-mv overdrive ? ? 90 ns sid337 [8] t comp2 response time low power mode, 50-mv overdrive ? ? 110 ns table 12. csd and idac block specifications spec id# parameter description min typ max units details/ conditions csd and idac specifications sys.per#3 vdd_ripple max allow ed ripple on power supply, dc to 10 mhz ? ? 50 mv vdd > 2v (with ripple), 25 c t a , sensitivity = 0.1 pf sys.per#16 vdd_ripple_1.8 max al lowed ripple on power supply, dc to 10 mhz ? ? 25 mv vdd > 1.75v (with ripple), 25 c t a , parasitic capaci- tance (c p ) < 20 pf, sensi- tivity 0.4 pf sid.csd#15 vrefhi reference buffer output 1.1 1.2 1.3 v sid.csd#16 idac1idd idac1 (8-bit s) block current ? ? 1125 a sid.csd#17 idac2idd idac2 (7-bit s) block current ? ? 1125 a sid308 v csd voltage range of operation 1.71 ? 5.5 v 1.8 v 5% or 1.8 v to 5.5 v sid308a vcompidac voltage comp liance range of idac 0.8 ? v dd ?0.8 v sid309 idac1 dnl dnl for 8-bit resolution ?1 ? 1 lsb sid310 idac1 inl inl for 8-bit resolution ?3 ? 3 lsb sid311 idac2 dnl dnl for 7-bit resolution ?1 ? 1 lsb sid312 idac2 inl inl for 7-bit resolution ?3 ? 3 lsb sid313 snr ratio of counts of finger to noise. guaranteed by characterization 5 ? ? ratio capacitance range of 9 to 35 pf, 0.1 pf sensitivity sid314 idac1 crt1 output current of idac1 (8 bits) in high range ? 612 ? a sid314a idac1 crt2 output current of idac1(8 bits) in low range ? 306 ? a sid315 idac2 crt1 output current of idac2 (7 bits) in high range ? 304.8 ? a sid315a idac2 crt2 output current of idac2 (7 bits) in low range ? 152.4 ? a sid320 idac offset all zeroes input ? ? 1 lsb sid321 idac gain full-scale error less offset ? ? 10 % sid322 idac mismatch mismatch between idacs ? ? 7 lsb sid323 idac set8 settling time to 0.5 lsb for 8-bit idac ? ? 10 s full-scale transition. no external load. sid324 idac set7 settling time to 0.5 lsb for 7-bit idac ? ? 10 s full-scale transition. no external load. sid325 cmod external modulator capacitor. ? 2.2 ? nf 5-v rating, x7r or np0 cap.
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 19 of 34 digital peripherals timer counter pulse-width modulator (tcpwm) i 2 c note 9. trigger events can be stop, start, reload, count, capture, or kill depending on which mode of operation is selected. 10. guaranteed by characterization. table 13. tcpwm specifications spec id parameter description min typ max units details/conditions sid.tcpwm.1 itcpwm1 block current consumption at 3 mhz ? ? 45 a all modes (tcpwm) sid.tcpwm.2 itcpwm2 block current consumption at 8 mhz ? ? 145 a all modes (tcpwm) sid.tcpwm.2a itcpwm3 block current consumption at 16 mhz ? ? 160 a all modes (tcpwm) sid.tcpwm.3 tcpwm freq operating frequency ? ? fc mhz fc max = clk_sys. maximum = 16 mhz sid.tcpwm.4 tpwm enext input trigger pulse width 2/fc ? ? ns for all trigger events [9] sid.tcpwm.5 tpwm ext output trigger pulse widths 2/fc ? ? ns minimum possible width of overflow, underflow, and cc (counter equals compare value) outputs sid.tcpwm.5a tc res resolution of counter 1/fc ? ? ns minimum time between successive counts sid.tcpwm.5b pwm res pwm resolution 1/fc ? ? ns minimum pulse width of pwm output sid.tcpwm.5c q res quadrature inputs resolution 1/fc ? ? ns minimum pulse width between quadrature phase inputs. table 14. fixed i 2 c dc specifications [10] spec id parameter description min typ max units details/conditions sid149 i i2c1 block current consumption at 100 khz ? ? 25 a sid150 i i2c2 block current consumption at 400 khz ? ? 135 a sid.pwr#5 isbi2c i 2 c enabled in deep sleep mode ? ? 2.5 a table 15. fixed i 2 c ac specifications [10] spec id parameter description min typ max units details/conditions sid153 f i2c1 bit rate ? ? 400 kbps
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 20 of 34 memory system resources power-on reset (por) table 16. flash dc specifications spec id parameter description min typ max units details/conditions sid173 v pe erase and program voltage 1.71 ? 5.5 v notes 11. it can take as much as 20 milliseconds to write to flash. during this time the device should not be reset, or flash operatio ns will be interrupted and cannot be relied on to have completed. reset sources include the xres pin, softwa re resets, cpu lockup states and privilege violations, improper power supply levels, and watchdogs. make certain that these are not inadvertently activated. 12. guaranteed by characterization. table 17. flash ac specifications spec id parameter description min typ max units details/conditions sid174 t rowwrite [11] row (block) write time (erase and program) ? ? 20 ms row (block) = 64 bytes sid175 t rowerase [11] row erase time ? ? 13 ms sid176 t rowprogram [1 1] row program time after erase ? ? 7 ms sid178 t bulkerase [11] bulk erase time (16 kb) ? ? 15 ms sid180 [12] t devprog [11] total device program time ? ? 7.5 seconds sid181 [12] f end flash endurance 100 k ? ? cycles sid182 [12] f ret flash retention. t a ? 55 c, 100 k p/e cycles 20 ? ? years sid182a [12 ] flash retention. t a ? 85 c, 10 k p/e cycles 10 ? ? years table 18. power on reset (pres) spec id parameter description min typ max units details/conditions sid.clk#6 sr_power_up power supply slew rate 1 ? 67 v/ms at power-up sid185 [12] v riseipor rising trip voltage 0.80 ? 1.5 v sid186 [12] v fallipor falling trip voltage 0.70 ? 1.4 v table 19. brown-out detect (bod) for v ccd spec id parameter description min typ max units details/conditions sid190 [12] v fallppor bod trip voltage in active and sleep modes 1.48 ? 1.62 v sid192 [12] v falldpslp bod trip voltage in deep sleep 1.11 ? 1.5 v
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 21 of 34 swd interface internal main oscillator internal low-speed oscillator note 13. guaranteed by characterization. table 20. swd interface specifications spec id parameter description min typ max units details/conditions sid213 f_swdclk1 3.3 v ? v dd ? 5.5 v ? ? 14 mhz swdclk 1/3 cpu clock frequency sid214 f_swdclk2 1.71 v ? v dd ? 3.3 v ? ? 7 mhz swdclk 1/3 cpu clock frequency sid215 [13] t_swdi_setup t = 1/f swdclk 0.25*t ? ? ns sid216 [13] t_swdi_hold t = 1/f swdclk 0.25*t ? ? ns sid217 [13] t_swdo_valid t = 1/f swdclk ? ? 0.5*t ns sid217a [13] t_swdo_hold t = 1/f swdclk 1 ? ? ns table 21. imo dc specifications (guaranteed by design) spec id parameter description min typ max units details/conditions sid218 i imo1 imo operating current at 48 mhz ? ? 250 a sid219 i imo2 imo operating current at 24 mhz ? ? 180 a table 22. imo ac specifications spec id parameter description min typ max units details/conditions sid223 f imotol1 frequency variation at 24 and 32 mhz (trimmed) ??2%2 v ? v dd ? 5.5 v, and ?25 c ? t a ? 85 c sid223a f imotolvccd frequency variation at 24 and 32 mhz (trimmed) ? ? 4 % all other conditions sid226 t startimo imo startup time ? ? 7 s sid228 t jitrmsimo2 rms jitter at 24 mhz ? 145 ? ps table 23. ilo dc specifications (guaranteed by design) spec id parameter description min typ max units details/conditions sid231 [13] i ilo1 ilo operating current ? 0.3 1.05 a sid233 [13] i iloleak ilo leakage current ? 2 15 na table 24. ilo ac specifications spec id parameter description min typ max units details/conditions sid234 [13] t startilo1 ilo startup time ? ? 2 ms sid236 [13] t iloduty ilo duty cycle 40 50 60 % sid237 f ilotrim1 ilo frequency range 20 40 80 khz
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 22 of 34 note 14. guaranteed by characterization. table 25. external clock specifications spec id parameter description min typ max units details/conditions sid305 [14] extclkfreq external clock input frequency 0 ? 16 mhz sid306 [14] extclkduty duty cycle; measured at v dd/2 45 ? 55 % table 26. block specs spec id parameter description min typ max units details/conditions sid262 [14] t clkswitch system clock source switching time 3 ? 4 periods
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 23 of 34 ordering information the psoc 4000 part numbers and features are listed in the foll owing table. all package types are available in tape and reel. part numbering conventions psoc 4 devices follow the part numbering convention described in th e following table. all fields are single-character alphanume ric (0, 1, 2, ?, 9, a,b, ?, z) unless stated otherwise. the part numbers are of the form cy8c4abcdef- xyz where the fields are defined as follows. category mpn feature package max cpu speed (mhz) flash (kb) sram (kb) capsense 7-bit idac 8-bit idac comparators tcpwm blocks i2c 16 -wlcsp 8-soic 16-soic 16-qfn 24-qfn 28-ssop cy8c4013 CY8C4013SXI-400 16 82????11? ? ???? cy8c4013sxi-410 16 82?11111? ? ???? cy8c4013sxi-411 16 82?11111?? ? ??? cy8c4013lqi-411 16 82?11111??? ? ?? cy8c4014 cy8c4014sxi-420 16 16 2 ? 11111? ? ???? cy8c4014sxi-411 16 16 2?11111?? ? ??? cy8c4014sxi-421 16 16 2 ? 11111?? ? ??? cy8c4014lqi-421 16 16 2 ? 11111??? ? ?? cy8c4014lqi-412 16 16 2?11111???? ? ? cy8c4014lqi-422 16 16 2 ? 11111???? ? ? cy8c4014pvi-412 16 16 2?11111????? ? cy8c4014pvi-422 16 16 2 ? 11111????? ? cy8c4014fni-421 16 16 2 ? 11111 ? ????? other cy8c4014lqi-slt1 16 16 2 ? 11111??? ? ?? cy8c4014lqi-slt2 16 16 2 ? 11111???? ? ? architecture cypress prefix family group within architecture speed grade flash capacity package code temperature range peripheral set 4: psoc 4 1: 16mhz 4: 16kb sx : soic i : industrial examples cy8c 4 a e d c bf x x - x 0 : 4000 family lq : qfn pv : ssop fn: wlcsp
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 24 of 34 the field values are listed in the following table: field description values meaning cy8c cypress prefix 4 architecture 4 psoc 4 a family 0 4000 family b cpu speed 1 16 mhz 448 mhz c flash capacity 3 8 kb 416 kb 532 kb 664 kb 7 128 kb de package code sx soic lq qfn pv ssop fn wlcsp f temperature range i industrial xyz attributes code 000-999 code of feature set in specific family
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 25 of 34 packaging table 27. package list spec id# package description bid#47a 28-pin ssop 28-pin 5 10 1.65mm ssop wit h 0.65-mm pitch bid#26 24-pin qfn 24-pin 4 4 0.6 mm qfn with 0.5-mm pitch bid#33 16-pin qfn 16-pin 3 3 0.6 mm qfn with 0.5-mm pitch bid#40 16-pin soic 16-pin (150 mil) soic bid#47 8-pin soic 8-pin (150 mil) soic bid#147a 16-ball wlcsp 16-ball 1.45 1.56 0.4 mm table 28. package characteristics parameter description conditions min typ max units t a operating ambient te mperature ?40 25 85 c t j operating junction temperature ?40 ? 100 c t ja package ja (28-pin ssop) ? 66.6 ? c/watt t jc package jc (28-pin ssop) ? 34 ? c/watt t ja package ja (24-pin qfn) ? 38 ? c/watt t jc package jc (24-pin qfn) ? 5.6 ? c/watt t ja package ja (16-pin qfn) ? 49.6 ? c/watt t jc package jc (16-pin qfn) ? 5.9 ? c/watt t ja package ja (16-pin soic) ? 142 ? c/watt t jc package jc (16-pin soic) ? 49.8 ? c/watt t ja package ja (16-ball wlcsp) ? 90 ? c/watt t jc package jc (16-ball wlcsp) ? 0.9 ? c/watt t ja package ja (8-pin soic) ? 198 ? c/watt t jc package jc (8-pin soic) ? 56.9 ? c/watt table 29. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature all 260 c 30 seconds table 30. package moisture sensitivity level (msl), ipc/jedec j-std-020 package msl all msl 3
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 26 of 34 package outline drawings figure 11. 28-pin ssop package outline figure 12. 24-pin qfn epad (sawn) package outline note 15. dimensions of the qfn package drawings are in millimeters. 51-85079 *f 001-13937 *f
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 27 of 34 the center pad on the qfn package should be connected to ground (vss) for best mechan ical, thermal, and electrical performance. if not connected to ground, it should be electrically floating and not connected to any other signal. figure 13. 16-pin qfn package epad (sawn) 001-87187 *a
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 28 of 34 figure 14. 16-pin (150-mil) soic package outline figure 15. 8-pin (150-mil) soic package outline note 16. dimensions of the qfn package drawings are in inches [millimeters]. 51-85068 *e 51-85066 *g
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 29 of 34 figure 16. 16-ball wlcsp 1.45 1.56 0.4 mm 001-95966 *a
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 30 of 34 acronyms table 31. acronyms used in this document acronym description abus analog local bus adc analog-to-digital converter ag analog global ahb amba (advanced microcontroller bus archi- tecture) high-performance bus, an arm data transfer bus alu arithmetic logic unit amuxbus analog mu ltiplexer bus api application programming interface apsr application program status register arm ? advanced risc machine, a cpu architecture atm automatic thump mode bw bandwidth can controller area network, a communications protocol cmrr common-mode rejection ratio cpu central processing unit crc cyclic redundancy check, an error-checking protocol dac digital-to-analog converter, see also idac, vdac dfb digital filter block dio digital input/output, gpio with only digital capabilities, no analog. see gpio. dmips dhrystone million instructions per second dma direct memory access, see also td dnl differential nonlinearity, see also inl dnu do not use dr port write data registers dsi digital system interconnect dwt data watchpoint and trace ecc error correcting code eco external crystal oscillator eeprom electrically erasable programmable read-only memory emi electromagnetic interference emif external memory interface eoc end of conversion eof end of frame epsr execution program status register esd electrostatic discharge etm embedded trace macrocell fir finite impulse resp onse, see also iir fpb flash patch and breakpoint fs full-speed gpio general-purpose input/output, applies to a psoc pin hvi high-voltage interrupt, see also lvi, lvd ic integrated circuit idac current dac, see also dac, vdac ide integrated development environment i 2 c, or iic inter-integrated circuit, a communications protocol iir infinite impulse response, see also fir ilo internal low-speed oscillator, see also imo imo internal main oscillator, see also ilo inl integral nonlinearity, see also dnl i/o input/output, see also gpio, dio, sio, usbio ipor initial power-on reset ipsr interrupt program status register irq interrupt request itm instrumentation trace macrocell lcd liquid crystal display lin local interconnect network, a communications protocol. lr link register lut lookup table lvd low-voltage detect, see also lvi lvi low-voltage interrupt, see also hvi lvttl low-voltage transistor-transistor logic mac multiply-accumulate mcu microcontroller unit miso master-in slave-out nc no connect nmi nonmaskable interrupt nrz non-return-to-zero nvic nested vectored interrupt controller nvl nonvolatile latch, see also wol opamp operational amplifier pal programmable array logic, see also pld table 31. acronyms us ed in this document (continued) acronym description
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 31 of 34 pc program counter pcb printed circuit board pga programmable gain amplifier phub peripheral hub phy physical layer picu port interrupt control unit pla programmable logic array pld programmable logic device, see also pal pll phase-locked loop pmdd package material declaration data sheet por power-on reset pres precise power-on reset prs pseudo random sequence ps port read data register psoc ? programmable system-on-chip? psrr power supply rejection ratio pwm pulse-width modulator ram random-access memory risc reduced-instruct ion-set computing rms root-mean-square rtc real-time clock rtl register transfer language rtr remote transmission request rx receive sar successive approximation register sc/ct switched capaci tor/continuous time scl i 2 c serial clock sda i 2 c serial data s/h sample and hold sinad signal to noise and distortion ratio sio special input/output, gpio with advanced features. see gpio. soc start of conversion sof start of frame spi serial peripheral interface, a communications protocol sr slew rate sram static random access memory sres software reset swd serial wire debug, a test protocol table 31. acronyms used in this document (continued) acronym description swv single-wire viewer td transaction descriptor, see also dma thd total harmonic distortion tia transimpedance amplifier trm technical reference manual ttl transistor-transistor logic tx transmit uart universal asynchronous transmitter receiver, a communications protocol udb universal digital block usb universal serial bus usbio usb input/output, psoc pins used to connect to a usb port vdac voltage dac, see also dac, idac wdt watchdog timer wol write once latch, see also nvl wres watchdog timer reset xres external reset i/o pin xtal crystal table 31. acronyms us ed in this document (continued) acronym description
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 32 of 34 document conventions units of measure table 32. units of measure symbol unit of measure c degrees celsius db decibel ff femto farad hz hertz kb 1024 bytes kbps kilobits per second khr kilohour khz kilohertz k ? kilo ohm ksps kilosamples per second lsb least significant bit mbps megabits per second mhz megahertz m ? mega-ohm msps megasamples per second a microampere f microfarad h microhenry s microsecond v microvolt w microwatt ma milliampere ms millisecond mv millivolt na nanoampere ns nanosecond nv nanovolt ? ohm pf picofarad ppm parts per million ps picosecond s second sps samples per second sqrthz square root of hertz vvolt
psoc ? 4: psoc 4000 family datasheet document number: 001-89638 rev. *e page 33 of 34 revision history description title: psoc ? 4: psoc 4000 family datasheet programmable system-on-chip (psoc ? ) document number: 001-89638 revision ecn orig. of change submission date description of change *b 4348760 wka 05/16/2014 new psoc 4000 datasheet. *c 4514139 wka 10/27/2014 added 28-pin ssop pin and package details. updated v ref spec values. updated conditions for sid174. updated sid.csd#15 values and description. added spec sid339. *d 4617283 wka 01/09/2015 corrected development kits information and psoc creator example project figure. corrected typo in the ordering information table. updated 28-pin ssop package diagram. *e 4735762 wka 05/26/2015 added 16-ball wlcsp pin and package details.
document number: 001-89638 rev. *e revised may 26, 2015 page 34 of 34 all products and company names mentioned in this document may be the trademarks of their respective holders. psoc ? 4: psoc 4000 family datasheet ? cypress semiconductor corporation, 2013-2015. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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